Local CBG Verilog and ECAD Tools

Here is information and sources for the CBG Verilog and ECAD tools.

See also the departmental Verilog Page and if you are a member of the Computer Laboratory cledahome .

There are two versions of the CBG Verilog compiler: CV2 and CV3. The mature version is CV2.18 which supports RTL, but not advanced behavioural constucts, such as conditional event control, is available for ftp below. The other version is CV3, which supports compilation of nearly the whole Verilog language but has some bugs which could be fixed if people are interested. Rather than fixing these bugs, I am instead working on C and Java to hardware compilers.

The Java compiler is designed to help portability of source code over the hardware-software divide and so can produce RTL Verilog or C depending on command line options. This compiler includes the behavioural compilation algorithms implemented in the CV3 based on the CX algorithm. To become a test site for these new tools please contact djg. Beyond the Java compiler, the next correct thing to do, in my belief, is to develop a tool that can compile a mixture of logical specification and behavioural/functional specification into a mixture of hardware and software. Anybody wishing to sponsor this activity, please make an offer.

• The manual for CV2.100 and CV3.100 will be placed here . These versions of the compiler are implemented in ML and are more advanced than the lisp versions. The advances include support for parameter overrides, compilation of arrays to memory blocks, generation of instances of adder and multiplier object blocks, function calls and many other language elements.

• This is the manual in postscript for the CSYN Verilog compiler CV2.18 and some other tools, incuding CVNL.

• Here are the sources for the CV2 Verilog Compiler (Release 2.18) in mar99, zip format . Anyone may experiment with this program. Contact DJG if you plan commercial use.

• Here are the sources for CVNL program which takes a Verilog net list, flattens it, and writes it out in various formats, including Verilog, Edif, Ranger 3 and Xilinx XNF format. mar99, zip format . With XNF output, this version has a new option to pass through unrecognised modules for later updating by xnfmerge. The EDIF output has been used to make Altera MaxPlus devices. Modified Jan 98 to include a slightly enhanced Verilog preprocessor.

• Here are the sources for LCATOV, a program which takes a routed Xilinx 3000 series .lca file and produces a Verilog model for it, including the tracking delays: unix tar.Z format . Contact djg for 4000 series equivalent program.

• Here are the library files for use with the above programs library directories .

• Here is the documentation on the Fourpie Teaching Cards (PS). Full documentation is on the local machine Thor in the directory djg11/fourpie.

• Here is the CSIM simulator user manual in postscript.

• Here is the Verilog to C compiler: VTOC .

Copyright for the software available on this web page belongs to DJ Greaves. This software may not be sold or used commercially without license. Also, no responsibility is taken for any bugs or consequential loss. Contact djg for details.