HOME
UP
  PREV
NEXT (Custom Accelerators on SoC or ASIC)
H/W to S/W Interfacing Techniques
The term `Programmed I/O' can refer to either MMIO or PMIO. These are the main alternative to I/O performed by DMA.
A note on terms:
- Port-mapped I/O (PMIO) refers to a special address space outside of normal memory that is accessed with instructions such as IN and OUT.
- Memory-mapped I/O (MMIO) refers to I/O devices being allocated addresses inside the normal Von Neumann address space
that is primarily used for program and data. Such I/O is done using instructions such as LOAD and STORE.
PMIO was very useful on A16 microprocessors since valuable address space was not consumer by the I/O devices, but A32 architectures
generally provide no PMIO instructions and hence use MMIO.
An accelerated system is divided into some number of hardware and software blocks with appropriate means of interconnection.
The primary ways of connecting hardware to software are:
- CPU coprocessor and/or custom instructions,
- Packet channel connected as coprocessor or mapped to main register file,
- Programmed I/O to pin-level GPIO register,
- Programmed I/O to FIFOs,
- Interrupts (hardwired to one core or dynamically dispatched),
- Pseudo-DMA: processor generates memory addresses or network traffic and the accelerator simply snoops or interposes on the data stream,
- DMA - Autonomous unit, much like a CPU in its own right.
Another design point is to do everything in hardware with no CPUs, but a CPU in a supervisorary role is normally sensible.