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Synthesis Example

How do we compile synthesisable RTL to gates?

Example input: 
module TC(clk, cen);
  input clk, cen;
  reg [1:0] count; 
  always @(posedge clk) if (cen) count<=count+1;
endmodule

Results in structural RTL netlist: 

module TC(clk, cen);
  wire u10022, u10021, u10020, u10019;
  wire [1:0] count;
  input cen;   input clk;
  CVINV  i10021(u10021, count[0]);
  CVMUX2  i10022(u10022, cen, u10021, count[0]);
  CVDFF  u10023(count[0], u10022, clk, 1'b1, 1'b0, 1'b0);
  CVXOR2  i10019(u10019, count[0], count[1]);
  CVMUX2  i10020(u10020, cen, u10019, count[1]);
  CVDFF  u10024(count[1], u10020, clk, 1'b1, 1'b0, 1'b0);
endmodule
Here the behavioural input was converted, by a Logic Synthesis Compiler, also known as an RTL Compiler, to an implementation technology that included inverters, multiplexors, D-type flip-flops and XOR gates.

For each gate, the output is the first-listed terminal.

20: (C) 2008-17, DJ Greaves, University of Cambridge, Computer Laboratory. Flash Player Upgrade Needed   PLAY/PAUSE  READY    STOP DOWNLOAD