HOME       UP       PREV       NEXT (Basic Physics)  

Part II CST SoC D/M Slide Pack 2 (Power)

  • Power, Performance and Technology
  • Basic Physics
  • Chip Dissipation and Delay
  • Detailed Delay Model.
  • Semi-Custom Design (repeated slide)
  • Detailed Power Model.
  • Typical Numerical Values
  • Save Power 1: Dynamic Voltage and Frequency Scaling
  • DVFS Example
  • 90 Nanometer Gate Length.
  • Deep submicron and Dark Silicon
  • Voltage Operating Point Adjustment
  • Power Saving Techniques Overview
  • Save Power 2: Dynamic Clock Gating
  • Save Power 3: Dynamic Supply Gating
  • DVFS in Low Leakage Technology
  • Static and Dynamic Power Tradeoff
  • Future Trends