A microprocessor logic symbol and minimal internal structure.
This device is a bus master or initiator of bus transactions.
It makes a load/read by asserting host read enable: hren.
It writes to addess space (a store) by asserting host write enable hwen.
In this course we are concerned with the external connections only.
| 6: (C) 2008-17, DJ Greaves, University of Cambridge, Computer Laboratory. |