ECAD and Architecture Practical Classes
ECAD and Architecture Labs are Hardware practicals designed for Part IB Computer Scientists.
Overview
These laboratory sessions will introduce you to a typical work-flow for hardware development on the tPad FPGA board.
The Labs have been designed to be undertaken in conjunction with the Computer Design course for Part IB students. They require knowledge gained from this course - mostly SystemVerilog and a processor covered in the course. It is strongly recommended that you look over the Labs before attending them, since you will only have a fixed amount of time with a demonstrator present to complete the practical.
Altera/Terasic competition
Innovation Europe competion organised by Altera and Terasic. Closing date for registration: 31st December. Free hardware to teams. Do talk to Simon Moore of you are interested in having a go. For further details see: http://www.innovateeurope.org/eu/
Supported by
- Prerequisite Learning
- SystemVerilog Tutor
- SystemVerilog Cheat Sheet (PDF)
- Introduction to C
- Background Information
- tPad
- Thacker's Tiny Computer (TTC)
- Development Guide
- Laboratory Work
- Lab 1
- Lab 2
- Deadlines
- Additional Information
- Troubleshooting
- Bluespec SystemVerilog
- Bluespec SystemVerilog Tutor
- Tick List
- Computer Design Lectures