reg q; input set, clear; always @(posedge set) q = 1; always @(posedge clear) q = 0;
Here a variable is updated by more than one thread.
This component is used mainly in specialist phase-locked loops. It can be modelled in Verilog, but is not supported for Verilog synthesis.
22: (C) 2008-13, DJ Greaves, University of Cambridge, Computer Laboratory. | Flash Player Upgrade Needed ![]() ![]() | ![]() |