Level 1/3: Structural Verilog: a structural netlist with hierarchy.
module subcircuit(clk, rst, q2); input clk, rst; output q2; wire q1, q3, a; DFFR Ff_1(clk, rst, a, q1, qb1), Ff_2(clk, rst, q1, q2, qb2), Ff_3(clk, rst, q2, q3, qb3); NOR2 Nor2_1(a, q2, q3); endmodule
Just a netlist.
There are no assignment statements that transfer data between registers in structural RTL (but it's still a form or RTL).
10: (C) 2008-13, DJ Greaves, University of Cambridge, Computer Laboratory. | Flash Player Upgrade Needed ![]() ![]() | ![]() |