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Clock Frequency Multiplier PLL and Clock Tree

Clock sourced from a lower-frequency external (quartz) reference.
Multiplied up internally with a phase-locked loop.
Dynamic frequency scaling (future topic) implemented with a programmable division ratio.
Skew in delivery is minimised using a balanced clock distribution tree.
Physical layout: fractal of H's, ensuring equal wire lengths.
Inverters are used to minimise pulse shrinkage (duty-cycle distortion).
Clock may be gated at the leaves before sending to idle flip-flops to save power.