SoCDAM Learners' Guide: and post-hoc lecture notes.
In my last lecture, I promised to update this guide by making it much clearer, more-specific and
twice as long. I am changing it now and this will be completed on 29th April 2009. .
Practical work : PRACTICALS.
OLD VERSION: LECTURE BY LECTURE POST HOC.
If people email me questions then I am more than happy to answer
them and I expect to place both the questions and the answers on
this FAQ.
LG1: RTL
LG1 NOTES covering:
- Introduction to the course and what a SoC is.
- Review/revision of Verilog: structural RTL, synthesisable RTL and
non-synthesisable constructs.
- What is synthesisable RTL? Look at its AST!
- An RTL program can be used both for simulation and synthesis.
- Adder and multiplier structures.
- Memories and other pipeline hazards.
- Automatic retiming.
LG2 SystemC
LG2 NOTES covering:
- It's history, overview, and how to use SystemC on the PWF.
- SystemC Components
- Example (Counter)
- SystemC Structural Netlist
- SystemC Signals
- Threads and Methods
- Blocking and Eventing
- Pre-TLM S/W Style Channels
- SystemC Synthesis
(NB: Question SC2 part c cannot be answered by everyone because the future developments
material was not lectured.)
LG3: System on Chip Design.
LG3 NOTES covering:
We learn about simple I/O blocks and how they implement
target-side, RTL-style bus interfaces and how they generate
interrupts. Looked at circular buffer device
driver for UART.
We look at further I/O blocks, discuss overrun/underrun
and the desire to minimise staging RAMs and FIFOs. We look at details of
an address decoder and simple bus structure in SystemC, with a full,
worked example called nominalprocessor.
- Overview of bus structure in an example SoC.
- Microcomputer from 1975 era: A16/D8 processor core and its address decode.
- Programmed I/O
- General Interrupt Structure
- General Purpose I/O Pins (GPIO)
- Other blocks: keyscan, timer, framestore.
- DMA Controller.
- Network Devices.
- A first look at a bus bridge.
LG4: ESL (Electronic System Level) Design.
LG4 NOTES covering:
- Motivation 1: Architectural Exploration
- Embedded Firmware Modelling Methods
- Example H/W Protocol: 4P Handshake
- What is a transaction ?
- Adding Timing Annotations
- TLM in SystemC: TLM 1.0
- SoC Component, TLM Form Example DMA Controller
- TLM in SystemC: TLM 2.0
- Timing Models
- Approximate Timing
- Loose Timing and Temporal Decoupling
LG5: Assertion Based Design.
LG5 NOTES covering:
- ABD versus the main alternative: Simulation
- Formally Synthesised Bus Monitor
- PSL Assertion, General Structure
- PSL Extended Regular Expressions
- Naive pattern to RTL Automaton
- PSL Overall Layered Architecture
- A Simple Model Checker
- Boolean Equivalence Checker
- Sequential Logic Equivalence and Simplification
- Automated Stimulus Generation
LG6: SFT Miscellany
LG6 NOTES covering:
Bus Structures, Design Flow and Tools.
- Throughput of Bridged Bus Systems.
- Network On Chip.
- An on-chip IP protocol with temporal decoupling: OCP BVCI.
- Memory subsystems: DRAM & Controller, Caches and Memory Macrocell Generator.
- Dynamic Clock Gate Insertion.
- Test Program Generator.
- Scan Path Insertion and JTAG standard test port.
- Cell Library Tour.
- ASIC Design flow: Signoffs prior to `Tapeout'.
- Manufacturing Industry Taxonomy.
LG7: Recent Developments
Not lectured in 2009.
LG8: Engineering
LG8 NOTES covering electronic engineering and physical limits.
- 90 Nanometer Gate Length.
- Power Consumption
- Dynamic Power Gating
- Dynamic Frequency Scaling
- Dynamic Voltage Scaling
- Information Flux
OLD LEARNERS GUIDE: LECTURE BY LECTURE POST HOC.
Worked and Running Examples
The material covered this year is organised into six classes.
1. Structural Netlists in SystemC.
2. The simple FIFO example from the SystemC Library.
3. The nominal processor ISS, extended as an RTL component.
4. The nominal processor ISS, extended as a loose-timed TLM component (TLM 1.0 style).
5. Two nominal processors plus bus arbiter.
6. DMA Controller.
PRACTICALS.