Many of the circuits used in the Fairisle project incorporate Xilinx chips. The configuration data for these chips is generally held on a small 8-pin serial PROM, which initialises the Xilinx on power-up. During testing, however, the Xilinx configuration may need to be changed several times, requiring many PROMs to be blown and then discarded.
The RAMPROM system allows a Xilinx Teaching Board (XTB), by means of a special
cable, to be plugged into the socket normally occupied by a Xilinx serial
prom. An emulator configuration is loaded into the XTB. The RAM
on the XTB can then be loaded with the data that would normally
be blown into the serial prom.
Here are some details of important files: