psfig

DAN Processor Node: The MDH-9
Design and Ideas

Mark Hayter

16th February, 1993
15th March 1994

The DAN project is investigating building a multimedia workstation based around the Desk Area Network. One area for investigation is the use of a DAN for processor to memory interconnect. A processor node, known as the MDH-9, is being designed around the ARM600 RISC processor. This node will have only a small amount of local memory and it is intended that, through the use of a cache, all of its main memory will be served across the DAN. The main parts of the processor node are shown in figure 1.

 
Figure 1:   Overview of DAN processor node

Technical updates have been done to this document for the 1994 documentation snapshot (the Blue Book). For results using the DAN CPU node and a higher level description of the card see technical report 319.

• The Processor Node
• Memory map
• Timing and Reset
• The cache
• Perhaps Interface
• Cache controller
• Status LEDs
• The 68901
• Links
• BOS software
• Pcb and PALs
• Appendix - code to size/shape the cache
• About this document ...