The interrupt handler, or FIQ, is a hand crafted assembler routine which is responsible for forwarding the cells through the port controller. This is a low latency interrupt, which runs asynchronously to the Wanda networking management code - that is it is not disabled even during a Wanda critical section. In order to further improve the latency of FIQ interrupt response the ARM provides six banked registers which are only accessible in FIQ mode and which may be used both to preserve state from one FIQ to the next and to avoid having to save registers before use.
The IOC provides the interrupt request and masking facility for the FIQ. The eight possible interrupt sources are detailed in table 3. Normally only the three interrupts generated by the xilinx chip are used. All interrupts may be individually masked.
The meanings of the interrupts and the actions of the interrupt software are highly dependent on the xilinx hardware in use, and are described in the appropriate document.
The port controller's operating speeds are 100Mbits/sec on the network
interface and 20MBytes/sec
on the fabric
interface. There is one frame pulse every 64 clock periods. A cell
could arrive on the transmission interface every 4.24us. A frame pulse
occurs every 3.2us. Additionally NACKs could
occur on 60% of cells at saturation.
The ARM3 operates on a 25MHz FCLK and a MCLK configurable as in table 11.
The ARM3 contains a 4K cache and when executing or fetching data from
the cache is able to complete such a cycle in one FCLK. The ARM cache is write through
and so on a write to memory or an access to an I/O device an external
cycle is required. The ARM synchronises to MCLK performs the cycle and
resynchronises to FCLK. The synchronising takes between 0 and 1 FCLK
and between 1 and 2 MCLKs. The resynchronising takes between 0 and 1
FCLK. All external cycles require one MCLK ``latent'' thus an external
DRAM write cycle takes 2 MCLKs, an access to the IOC 3 MCLKs and an
access to the Xilinx chip with the ``slowarm'' interface (currently
used for all designs) takes 4 MCLKs. Based on an 8.33MHz MCLK on
average a DRAM write cycle, an IOC access and a Xilinx access take
460ns, 580ns and 700ns respectively. These are a long time compared
with an FCLK period of 40ns.
The ARM600 which is used on some FPC2 cards and the ARM610 used on the FPC3
runs at 25 MHz FCLK, but (due to a bug
on the chip) requires a special relationship between MCLK and FCLK,
requiring use of 8.33MHz MCLK. These newer processors are faster at
synchronising between the clocks and contain a write buffer which
enables the CPU to continue to run from its internal clock while
writing to external devices.