FPL 2015, Half Day Tutorial
August 31st 2015, Imperial College, London, UK
The NetFPGA is an open platform enabling researchers and instructors to build high-speed, hardware-accelerated networking systems. The NetFPGA is the de-facto experimental platform for line-rate implementations of network research and it has a family of boards, supporting from 1GE to 100GE. This half-day tutorial will provide an introduction to prototyping and using networking devices on the NetFPGA platform, and discuss considerations in architecture and design for high bandwidth devices.
The demand-led growth of cloud computing and datacenter networks has meant that many constituent technologies are beyond the budget of the research community. In order to make and validate timely, relevant research contributions, the wider research community requires accessible evaluation, experimentation and demonstration environments with specification comparable to the subsystems of the most massive datacenter networks.
The NetFPGA is an open platform enabling researchers and instructors to build high-speed, hardware-accelerated networking systems. The platform can be used by researchers to prototype advanced services for next-generation networks. It can also be used in the classroom to teach students how to build Ethernet switches and Internet Prototcol (IP) routers using hardware rather than software. The most prominent NetFPGA success is OpenFlow, which in turn has reignited the Software Defined Networking movement. NetFPGA enabled OpenFlow by providing a widely available open-source development platform capable of line-rate operation and was, until its commercial uptake, the reference platform for OpenFlow.
This tutorial will focus on rapid prototyping of high bandwidth devices, using flexible, open-source IPs. It will present NetFPGA SUME, an open-source FPGA-based PCIe board, designed for the research community. NetFPGA SUME has I/O capabilities for 100Gbps operation as a networking device, stand alone computing unit or for test and measurement. In addition we will also present the NetFPGA-1G-CML platform, which enables complex designs for low-bandwidth applications, especially suited for network-security applications.
The tutorial will give the participants an opportunity to experience the prototyping of a working hardware networking application. It will also provide a live demonstration of a high-bandwidth networking device. The target audience is not restricted to networking researchers: the NetFPGA provides the ideal platform for research across a wide range of topics from computing architecture to algorithms, and from energy-efficient design to hardware accelerators. It is thus ideally suited for the attendees of FPL. No knowledge of Verilog/VHDL is required to attend the tutorial, although knowledge of these languages is needed to program NetFPGA.
Dates: August 31st, 2015 (Monday)
Time: 9:00 - 12:30
Location: Imperial College London's South Kensington campus, London, UK
More information: here.
Short bio of our Tutors:
Andrew W. Moore is a Senior Lecturer at the University of Cambridge Computer Laboratory in England, where he is part of the Systems Research Group working on issues of network and computer architecture. His research interests include enabling open-source network research and education using the NetFPGA platform, other research pursuits include low-power energy-aware networking, and novel network and systems data-center architectures. He holds B.Comp. and M.Comp. degrees from Monash University and a Ph.D. from the University of Cambridge. He is a chartered engineer with the IET and a member of the IEEE, ACM and USENIX.
Noa Zilberman is a Research Associate at the University of Cambridge Computer Laboratory in England. Zilberman has over 15 years of industrial experience in the telecommunication and semiconductor industries. In her last role, Zilberman was a senior principal chip architect in Broadcom’s Network Switching group.
Her research interests include open-source research using the NetFPGA platform, switching architectures, high speed interfaces, network measurements and Internet topology.
Zilberman is a Senior Member of IEEE, a member of ACM and Usenix, and has a PhD in Electrical Engineering from Tel Aviv University.
Yury Audzevich is a Research Associate at the University of Cambridge Computer Laboratory in England.
He is an expert on energy-efficient designs for high-bandwidth networking devices, and was the lead researcher of CONTEST (CONfigurable Transceiver Energy uSage Toolkit). Previously, he was an Alcatel-Lucent Research Associate at the University of Trento.
His current research interests lie in the field of reconfigurable systems, circuit design and energy-efficiency aspects in communication architectures.
Audzevich obtained his PhD in Information and Telecommunication technologies from the University of Trento.
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