Friday, June 15, 2012
9am - 5pm
Department of Computing,
Imperial College London,
Room 343, 3rd Floor
180 Queen's Gate, London, SW7 2RH, UK
The NetFPGA is and open platform enabling researchers and instructors to build high-speed, hardware-accelerated networking systems. The platform can be used in the classroom to teach students how to build Ethernet switches and Internet Prototcol (IP) routers using hardware rather than software. The platform can be used by researchers to prototype advanced services for next-generation networks.
By using Field Programmable Gate Arrays (FPGAs), the NetFPGA enables new types of packet routing circuits to be implemented and detailed measurements of network traffic to be obtained. During the tutorial, attendees will learn about the NetFPGA platform and and how it can be used. We will demonstrate the use of the reference router to dynamically re-route traffic using PW-OSPF with streaming video traffic. We will also show how we can extend existing designs to experiment with buffer sizes.
No knowledge of Verilog/VHDL is required to attend the tutorial, although knowledge of these languages is needed to program NetFPGA.
Introduction to the Platform
Users (Professors & Researchers)
What is the NetFPGA
Brief recap if IP/Routing
Example 1: Basic Functionality (reference router)
Example 2: Advanced Functionality (buffer sizing based on reference router)
Brief introduction of buffer sizing
Where to get started/What to do next
Andrew completed his Ph.D. with the Cambridge University Computer Laboratory in 2001 and prior to that took a Masters degree and an honours degree from Monash University in Melbourne. Australia. Alongside routine collaboration with AT&T, Endace, Intel, and Microsoft, Andrew Moore has served as principal investigator on grants from the UK Research Council (EPSRC), a number of other UK government bodies and acts as investigator on two DARPA grants. He is a chartered engineer with the IET and a member of the IEEE, ACM and USENIX.
Andrew lead the recently completed Alpha-user programme for the new, 10Gbps NetFPGA.