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2b/3: Pure RTL : unordered synchronous register transfers.

Two coding styles (it does not matter whether these transfers are each in their own always statement or share over whole clock domain):
always @(posedge clk) a <= b ? c + d; always @(posedge clk) b <= c - d; always @(posedge clk) c <= 22-c;
// or always @(posedge clk) begin a <= b ? c + d; b <= c - d; c <= 22-c; end

In System Verilog we would use always_ff in the above cases.

Typical example (illustrating pure RT forms):

    module CTR16( 
      input mainclk, 
      input din,
      output o);
 
      reg [3:0] count, oldcount;
 
      always @(posedge mainclk) begin
          count <= count + 1;
          if (din) oldcount <= count; // Is `if' pure ?
          end

     // Note ^ is exclusive-or operator
     assign o = count[3] ^ count[1];

   endmodule

Registers are assigned in clock domains (one shown called `mainclk'). Each register is assigned in exactly one clock domain. RTL synthesis does not generate special hardware for clock domain crossing (described later).

In a stricter form of this pure RTL, we cannot use `if', so when we want a register to sometime retain its current value we must assign this explicitly, leading to forms like this:

   oldcount <= (din) ? count : oldcount;