RAM Memories in RTL

RTL supports arrays and these arrays can be synthesised to RAM memories or register files.

    reg [31:0] myram [32767:0];  // 32K words of 32 bits each.
    // To execute the following in one clock cycle needs two RAM ports
    always @(posedge clk) myram[a] <= myram[b] + 2;

Today: RAM inference from array is only done by FPGA tools and high-level synthesis tools. Everyone else (ASIC and PCB designers) defines busses and makes structural instances.

Example dual-ported (one read, one write), SRAM behavioural model:

  module R1W1RAM(din, waddr, clk, wen, raddr, dout);
    input clk, wen;
    input [14:0] waddr, raddr;
    input [31:0] din;
    output [31:0] dout; 

    reg [31:0] myram [32767:0];  // 32K words of 32 bits each.
    always @(posedge clk) begin
         dout <= myram[raddr];
         if (wen) myram[waddr] <= din;
         end

The behavioural model will be replaced with a RAM macrocell in the silicon implementation.