HLS removes instruction-fetch and decode entirely. Custom register lengths also commonly used.
»A Survey and Evaluation of FPGA High-Level Synthesis Tools, Nane et al, IEEE T-CAD December 2015|
Kiwi (Greaves/Singh) Scientific Accelerator: C\# programs are implemented on FPGA for high-performance with low energy.
| 9: (C) 2012-17, DJ Greaves, University of Cambridge, Computer Laboratory. |