Much more to context switch.
Banking/barelling the FPGA/CGRA configuration is certainly an option: even considered within a single design for spatial folding to TDM (Rosemary Francis PhD + Guy Lemieux).
Microsoft Azure ameliorates this by decoupling the FPGA from the blade. One blade oversees the FPGA's on many neighbouring blades using local interconnect. FPGAs are left semi-permanently configures for one application such as Bing.
Michael Dales Phd Thesis addressed this first: »Managing a Reconfigurable Processor in a General Purpose Workstation Environment - Date 2003
| 12: (C) 2012-17, DJ Greaves, University of Cambridge, Computer Laboratory. |