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Detailed Delay Model.

images/sethold.png images/critical.png

The maximum clock frequency of a synchronous clock domain is set by its critical path.

Logic net with tracking and input load capacitances illustrated. Both the power consumption and effective delay of a gate driving a net depend mainly on the length of the net driven. Capacitive loading of a gate:

the capacitance proportional to the area of the output conductor,
the sum of the input capacitances of the devices fed.

Total gate delay is then:

the internal delay of the gate, termed the intrinsic delay
the derating owing to the fanout loading,

   device delay = (intrinsic delay) + (output load x derating factor).

The track-dependent output loading is a library constant times the track area.

The load-dependent part is the sum of the input loads of all of the devices being fed.

For short, non-clock nets (less than 0.1 wavelength), include propagation delay in the gate derating and assume the signal arrives at all points simultaneously.

Only know track length post layout. Pre-layout and pre-synthesis we can predict net lengths from Rent's Rule and RTL-level heuristics.