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Voltage Operating Point Adjustment

The FO4 delay is the delay of one inverter when driving four others over the minimal amount of wiring.

CMOS logic delay is inversely proportional to supply voltage. For instance:

images/vccderate.png
Delay is approximately proportional to ( C * V ) / ( (V-Vt) ^ 2)
Epiphany 16 Core `Supercomputer' Chip DVFS Points (a plot, not a table).
29: (C) 2012-18, DJ Greaves, University of Cambridge, Computer Laboratory.