NoC Modelling

Do we want to model every contention point and queuing detail ?

Use a high-level model: Treat the NoC just as a square array corresponding to the floor plan of the chip and in each entry we hold a running average local utilisation.

• Add delay penalty to traversing transaction based on 1/(1-p), »Computer Systems Modelling
• Log local energy consumption proportional to delay,
• Target routing protocol can be used unmodified or skipped.

Or model even more abstractly: uses »Rent's Rule estimate of average communication length assuming a `sensible' layout.

Avoid a detailed layout: Rent's rules of thumb predict the number of connections per sub-system and reflect the expected reduction in average wire length arising from good design and layout compared to a random collection of components.

Problems with higher than cycle-accurate modelling:

• Transactions may be out of order if using large quantum L/T model (see later).
• Deadlock may be missed.