Generally speaking, High-Level Synthesis (HLS) compiles software into hardware.

Basic Steps of an HLS Flow.

Although a research topic for decades, HLS is now seeing industrial traction.

An HLS system revolves around an HLS compiler for a high-level language (typically C++). This

• Binds HLL arrays to RAMs and base addresses to items stored in a common RAM.
• Decides what mix of structural components (FUs) such as RAMs and ALUs to instantiate.
• Allocates work to clock cycles (aka schedulling).
• Generates an RTL output for the logic synthesis.
• May provide pre-built libraries for common I/O and mathematics.

The output from an High-Level Synthesis (HLS) compiler is generally RTL which is then fed to an RTL compiler, aka Logic Synthesiser, that performs logic synthesis. As we have seen, the logic synthesizer

• instantiates multiplexors that transfer data according to predicates.
• performs logic minimisation or area/power optimisation.
• expands operations on broadside (aka vector) registers into simple boolean operations (aka bit blasting).
• replaces simple boolean operators with gates from an ASIC cell library or look-up tables in an FPGA.

Traditional RTL design entry (Verilog/VHDL) needs:

• Human comprehension of the state encoding,
• Human comprehension of the cycle-by-cycle concurrency, and
• Human accuracy to every low-level detail, such as which registers are live.

Performing a Time-for-Space re-folding (i.e. doing the same job with more/less silicon over less/more time) requires a complete redesign when entered manually in RTL!

Optimising schedules in terms of memory port and ALU uses ? RTL requires us use Pen and paper?

Can we do better than manual RTL coding ? Yes, we use High-Level Synthesis.

Dark silicon facilitates `Conservation Cores'. A paper at ASPOLOS'10 about putting common kernels in silicon and `Reducing the Energy of Mature Computations' by power gating. »PDF