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Video Controller: Framestore

 
  reg [3:0] framestore[32767:0];
  reg [7:0] hptr, vptr; 
  output reg [3:0] video;
  output reg hsynch, vsynch;

  always @(posedge clk) begin
       hptr <= (hsynch) ? 0: hptr + 1;
       hsynch <= (hptr == 230) 
       if (hsynch) vptr <= (vsynch) ? 0: vptr + 1;
       vsynch <= (vptr == 110) 
       video <= framestore[{vptr[6:0], hptr}];

       if (hwen) framestore[haddr]<= wdata[3:0];
       end

Alternate design uses private SRAM instead of main system RAM (share instead with staging FIFO?).

The pixel clock rate, H/W dimensions and synch pulse widths are normally programmable.

The RAM cannot be read. Moreover it has two address ports: re-code with one arbitrated port ?

26: (C) 2011-12, DJ Greaves, University of Cambridge, Computer Laboratory.