The DAN processor node is based on the ARM600 processor. This is a derivative of the ARM series of processors that are used in the Fairisle port controller. It uses the ARM6 macro cell with a 4k byte cache, a write-back buffer, and an MMU.
It is intended that the processor node run the Wanda microkernel. This requires a regular timer interrupt, mainly used to enable timeouts on semaphore operations. In addition, especially for use during debugging, it is usual for the console to be provided via a RS-232 serial line. To provide both of these a 68901 Multi-Function Peripheral chip will be put on the processor node. This chip was chosen because the Wanda device drivers have already been written for it, and we have a number in stock.
At least until the remote memory system has been debugged the processor node will require local memory to permit booting. Eventually it should be possible for all memory to be served but this is thought impractical for development of the remote system. Thus some ROM and some RAM will be provided on the node. It has been found that 128k bytes of ROM is borderline for fitting an ARM Wanda boot kernel, so it is intended to provide 256k through the use of four 27512 devices. The size of RAM provoked much discussion. Since it is only required for the development of the node, and was intended to be a ``small'' amount, it was thought that the additional complexity of using DRAM was not warranted. Therefore 512k bytes of SRAM are provided. There are two reasons for this size. It should be sufficient for the current boot system (which copies the ROM code and runs entirely out of RAM) (though there may be insufficient space to store the loaded image). It is also enough for a full set of MMU page tables to be kept in local memory (tr has suggested that this will take 256k).
The node will have network access, via a simple interface (the ``perhaps'' interface). This is based on a single cell deep transmit FIFO and a single cell deep receive FIFO. These connect directly to the DAN switch, and thus the rxFIFO not-empty condition can cause NACKs. This interface is not designed for high speed, it will be used for setting up connections to memory servers and infrequent RPC operations.
The main part of the node is the cache section. This provides access to remote memory for the processor node. The cache size has been chosen as 128k bytes, and the ATM cell size of 48 bytes suggests that a cache line of 32 bytes would be ideal. Expansion of the cache to 512k is permitted by the design, but there is only PCB space for 256k. Studies of cache systems have suggested that for such size the improvement in miss-ratio of going from direct mapped to 2-way set associative is sufficiently small that it does not justify the increase in complexity of the cache. In this case this argument is not valid - at least provided 2 way associativity does not require insertion of extra processor cycles in every memory access - since the cache line refill time is very large compared to the hit access time. Rough calculation suggests that the 0.5% change in miss-ratio is equivalent to increasing the average memory access time by more than one memory clock cycle. Thus the 128k of cache will be organised as two banks of 64k.