Accelerated verification challenges

Today, hardware designers and the EDA tool ecosystem face unprecedented innovation pressure, being offered abundant transistors, endless opportunities for specialization, and several high-demand domain-specific use cases. Breakthroughs in AI, formal methods, new compiler technology, and the potential for hardware to accelerate EDA create critical opportunities to deliver order-of-magnitude improvements to EDA. Identifying and exploiting such opportunities requires exploring novel tools, technology, and development approaches beyond evolving existing technology stacks.

Accelerating verification, the central hardware design bottleneck, and the systematic synthesis of novel hardware designs are the most promising areas for innovation. Together, these may lead to our ultimate moonshot goal: a ‘push button’ solution to EDA that takes high-level requirements and produces an optimised and fully verified hardware design. Verifying such auto-generated designs fast and reliably is a prerequisite for any significant increase in automation.

Simulation (plus testing based on simulation) is one of the most commonly used approaches to hardware verification. Yet, these simulations are highly redundant, as only a fraction of the computation offers new insights, while most performance is spent on recovering already known simulation states bringing an opportunity for order-of-magnitude improvements to simulator performance.

Accelerated hardware debug and pre-silicon software validation via hardware emulation systems has already demonstrated success. Yet further opportunities exist for hardware-accelerated verification based on domain-specific optimisations and insights from compiler analysis.

Challenges

• Can we make full-cycle simulation faster by exploiting speculation, multi-threading, acceleration via FPGA or even AI accelerators?
• How can we improve test-case stimulus generation to comprehensively test a hardware design, maximising coverage of the design under test while minimising the time taken to generate and execute tests?
• Can we build custom computer architectures that are optimised for code and memory-access patterns arising in hardware simulator applications, co-desiging hardware and software together or exploring trade-offs between performance and precision of the results?