Computer Architectures of the Future

PhD applicants to the University of Cambridge must write a research proposal, laying out details of the research they wish to undertake as part of the PhD. More information is available on the applications page. Research proposals from applicants to CASCADE must address one or more of the research challenges laid out below.

We are currently accepting applications to research future systems that look beyond the RISC paradigm to rethink the ISA abstraction. However, as the Centre expands in future years, we expect to broaden into other research areas.

Programs contain a significant amount of semantic information about their operation. Some of this is encoded through programming-language constructs, some is inferred by the compiler through static analysis, and some can be determined during execution by the runtime system. However, modern toolchains – by design – throw this information away as a program is compiled, leaving just the operations encoded in the processor's usually simple, RISC-based ISA. To obtain high performance during run-time, microarchitectures have to reconstruct this information, enabling them to predict how future execution will proceed. This results in significant use of transistors with associated power costs, in addition to complexity and performance overheads, when predictions are inevitably occasionally wrong.

While classical hard and software design trade-offs favoured a narrow interface between applications and hardware, there is no fundamental reason why application binaries must pass through a funnel where known information about a program has to be thrown away during the process of compiling and running it. In fact, if we could efficiently pass on this information to the processor, it could execute the application with knowledge of the future that it did not have to infer itself. In effect, by widening the communication channel between software and hardware we can build more efficient and less complex processors that can still take advantage of this future and know even more about the application than they can easily infer nowadays.

Challenges

• How can we make best use at run-time of data that the compiler currently throws away during compilation?
• How should information about an application be transferred from compiler to the processor?
• How might future microarchitectures change to take advantage of additional program information?
• Can future program information enable the microarchitecture to exploit new forms of parallelism?