Important dates
- 3 September 2025
- Applications open
- 2 December 2025
- Applications close
- 27 February 2026
- Notifications sent
- 1 October 2026
- Course starts
Research challenges
PhD applicants to the University of Cambridge must write a research proposal, laying out details of the research they wish to undertake as part of the PhD. More information is available on the applications page. Research proposals from applicants to CASCADE must address one or more of the research challenges laid out below. We currently have two research themes with broad challenges within them. However, as the Centre grows in future years, we expect to expand into other research areas.
Programs contain a significant amount of semantic information about their operation. Some of this is encoded through programming-language constructs, some is inferred by the compiler through static analysis, and some can be determined during execution by the runtime system. However, modern toolchains – by design – throw this information away as a program is compiled, leaving just the operations encoded in the processor's usually simple, RISC-based ISA. To obtain high performance during run-time, microarchitectures have to reconstruct this information, enabling them to predict how future execution will proceed. This results in significant use of transistors with associated power costs, in addition to complexity and performance overheads, when predictions are inevitably occasionally wrong.
While classical hard and software design trade-offs favoured a narrow interface between applications and hardware, there is no fundamental reason why application binaries must pass through a funnel where known information about a program has to be thrown away during the process of compiling and running it. In fact, if we could efficiently pass on this information to the processor, it could execute the application with knowledge of the future that it did not have to infer itself. In effect, by widening the communication channel between software and hardware we can build more efficient and less complex processors that can still take advantage of this future and know even more about the application than they can easily infer nowadays.
Challenges
We seek to improve the performance-efficiency of processors running existing compute-intensive workloads, written in industry-standard languages such as C and C++ without source-level modification. The overall aim is to consider how augmenting program binaries with performance-relevant semantic information can directly improve execution speed, resource utilization, or power usage.
- Are there aspects of program structure, data usage and dependencies, algorithmic insights, parallelism opportunities, and so on that the compiler knows about but currently discards during compilation, that we could make use of at run-time?
- How should relevant performance-enhancing program information be transferred from compiler to processor?
- How might conventional microarchitectures be extended to exploit this augmented information, without penalising performance and compatibility of non-augmented binaries?
- Can augmented program information enable exploitation of new forms of parallelism?
Today, hardware designers and the EDA tool ecosystem face unprecedented innovation pressure, being offered abundant transistors, endless opportunities for specialization, and several high-demand domain-specific use cases. Breakthroughs in AI, formal methods, new compiler technology, and the potential for hardware to accelerate EDA create critical opportunities to deliver order-of-magnitude improvements to EDA. Identifying and exploiting such opportunities requires exploring novel tools, technology, and development approaches beyond evolving existing technology stacks.
Accelerating verification, the central hardware design bottleneck, and the systematic synthesis of novel hardware designs are the most promising areas for innovation. Together, these may lead to our ultimate moonshot goal: a ‘push button’ solution to EDA that takes high-level requirements and produces an optimised and fully verified hardware design. Verifying such auto-generated designs fast and reliably is a prerequisite for any significant increase in automation.
Simulation (plus testing based on simulation) is one of the most commonly used approaches to hardware verification. Yet, these simulations are highly redundant, as only a fraction of the computation offers new insights, while most performance is spent on recovering already known simulation states bringing an opportunity for order-of-magnitude improvements to simulator performance.
Accelerated hardware debug and pre-silicon software validation via hardware emulation systems has already demonstrated success. Yet further opportunities exist for hardware-accelerated verification based on domain-specific optimisations and insights from compiler analysis.
Challenges
- Can we make full-cycle simulation faster by exploiting speculation, multi-threading, acceleration via FPGA or even AI accelerators?
- How can we improve test-case stimulus generation to comprehensively test a hardware design, maximising coverage of the design under test while minimising the time taken to generate and execute tests?
- Can we build custom computer architectures that are optimised for code and memory-access patterns arising in hardware simulator applications, co-desiging hardware and software together or exploring trade-offs between performance and precision of the results?
- How can we make more effective use of compiler analysis and transformations, including within intermediate representations such as MLIR, for digital simulation?