Simon's Projects 1998
Hardware Oriented Projects:
Electronic ornaments
Dataflow DSP
Geomentric HDL
Self-timed processor simulator
Animated Strong ARM
Animated circuits

Geometric Hardware Description Language

hardware/software ration=10:90


Today's popular hardware description languages (HDLs) typically discard locality information (e.g. VHDL, Verilog). Thus the router is given a sea of gates without any hints about critical paths. Consequently it performs a general optimisation on this huge mass of gates which takes a considerable time.

However, the designer often knows about critical paths. For example, if you are designing an adder then you know that the carry chain is a critical path. Thus, you would like to place carry generation logic of an adder in one locality. In fact the designer has probably specified the adder as one logical unit, but still the HDL throws this information away. These constraints may make the place and route simpler and, thus, faster.

There is probably at least one Ph.D. in this project. None the less, a simplified version could be developed and built upon by a good Tripos student.

Previous work

Satnam Sing in Glasgow is doing some work in this area. There is also a bissare stack based language with 2D program counter called Befunge!

Special resources


Possible supervisors

I'm willing to supervise this project.