Proposal
This project is to produce high level register transfer simulator
toolkit for to assist self-timed processor design. The toolkit would
include a discrete event simulator (i.e. timed message passing system)
and graphical output monitor routines to assist debugging.
This would contrast other systems (e.g. LARD - see below) which are a
language in themselves. The toolkit approach is far simpler and yet
more flexible than a custom language approach albeit at the risk of
reduced clarity (i.e. using the toolkit is likely to produce slightly
larger code). However, this might be rectified by preprocessing code
before compilation in order to replace compact syntactic sugar with
more verbose code ready for compilation.
A toolkit approach has another big advantage - efficiency - the
toolkit can be compiled with an industrial strength compiler where as
a custom language is more likely to be interpreted or use poor
compilation techniques due to lack of man effort to do any better.
Previous work
This is the first time I've proposed this project. However, I've
supervised many projects which revolved around a discrete event
simulator.
I very much like Phil Endecott's LARD
(Language for Asynchronous Research and Development) but I think a
simulation toolkit might be simpler (well, the complexity is already
solved by another language design team) and faster. Also, his
simulator won't go
backwards!
Special resources
None.
Possible supervisors
I'm willing to supervise this project.
|