Cell: joinpads1G © Simon Moore, 1997

Used By

None (top level cell)

Subcells Used

1 x chipoutsel
1 x contdata16G_v1
1 x contdyndata16G_v1
1 x event_G
16 x in1to2wire_v1
3 x inv16
4 x inv3
1 x logo
2 x outctrlG
1 x padringG
2 x simplebuf

Notes

Top level cell which wires up the large blocks to themselves and to the pad ring. Note that the pad ring can easily be removed to facilitate simulation since simulation models for pads were not available.

Key

metal 2
metal 1
polysilicon
via or contact
N+
P+
N well