Self-Timed Test Chip

Overview

As part of an EPSRC funded project on self-timed design, we designed and produced a small full custom test chip to check that novel self-timed components worked in practice. A good deal of the design work is described in a paper entitled RED Flip-Flops and Hybrid Completion Detection.

Links

• Look at the chip in detail
• Further details of the Self-Timed Logic Project