Comparative Architectures

• Overview
  This course compares a number of past and present microprocessor architectures, examining how various architectural features have affected implementation and use, and hence determined the architecture's longevity.
• Syllabus
  
  1. Comparing architectures. The technology curve. System versus chip performance. Speed: MIPS, MHz, FLOPS, SPEC. Power. Price. Compatibility. Features. (1.5 lectures)
  2. Instruction Set Architecture. Amdahl's law and RISC principles. Byte sex. Word size. Stacks, Accumulators and GPRs. Load-store versus Register-memory. Addressing modes. Code Density. Sub-word and un-aligned loads and stores. (2 lectures)
  3. Pipelining. The CPU performance equation. Structural hazards: long latency instructions. Data hazards: result forwarding and delayed loads. Control hazards: optimizing branches, and avoiding branches. Exceptions. (2 lectures)
  4. Instruction Level Parallelism. Super-scalar. Static scheduling and Dynamic out-of-order execution. Register renaming. The limits of ILP. (1.5 lectures)
  5. Memory hierarchy. Cache configurations. Latency versus bandwidth . Re-ordering and coherence. Programming for caches. (1 lecture)
• All lectured material is examinable, unless explicitly stated otherwise
• Highly recommended reading
  Hennessy, J. & Patterson, D. (1996). Computer Architecture: a Quantitative Approach (Chapters 1-5 in particular). Morgan Kaufmann (2nd ed.).
• Further reading and reference
  Tannenbaum, A.S. (1990). Structured Computer Organization. Prentice-Hall (2nd ed.).
  Van Someren, A. & Atack, C. (1994). The ARM RISC Chip: a Programmer's Guide. Addison-Wesley.
  Sites, R.L. (ed.) (1992). Alpha Architecture Reference Manual. Digital Press.
  Kane, G. & Heinrich, J. (1992). MIPS RISC Architecture. Prentice-Hall.
  Messmer, H. (1995). The Indispensable Pentium Book. Addison-Wesley.
• Material on the web
  The Berkeley CPU Info Center
  SPEC Benchmark organisation
• OHP Slides with additional notes (from 1998 course)
  mynotes.ps