ESL: Electronic System Level Modelling

We can model our hardware system at various levels of detail following the taxonomy:

• Functional Modelling: The `output' from a simulation run is accurate.
• Memory Accurate Modelling: The contents and layout of memory is accurate.
• Untimed TLM: No time stamps recorded on transactions.
• Loosely-timed TLM: The number of transactions is accurate, but order may be wrong.
• Approximately-timed TLM: The number and order of transactions is accurate.
• Cycle-Accurate Level Modelling: The number of clock cycles consumed is accurate.
• Event-Level Modelling: The ordering of net changes within a clock cycle is accurate.

An ESL methodology aims:

Aim 1: To model with good performance a complete SoC using full software/firmware.

Aim 2: To allow seamless and successive replacement of high-level parts of the model with low-level models/implementations when available and when interested in their detail.

So, an ESL methodology must provide:

• Tangible, lightweight rapidly-generated prototype of full SoC architecture.

• Rapid Architectural Evaluation: determine bus bandwidth and memory use for a candidate architecture. Easy to adjust major design parameters.

• Algorithmic Accuracy: Get real output from an early system, hosting the real application/firmware, possibly in real-time.

• Timing information: Get timing numbers for performance (accurate or loose timing).

• Power information: Get power consumption estimates to evaluate chip temperature and system battery life.

• Firmware development: Integrate high-level behavioural models of major components with their device drivers to run test software and applications.

Enhancements beyond that are:

• Synthesise high-level models to form parts of the fabricated system (e.g. using HLS)(but today manual re-coding is mainly used).
• Embed assertions in the high-level models and use these same assertions through to tape out.