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Delta Cycles are not examinable CST 15/16 onwards.
All three of VHDL, Verilog RTL and SystemC support the compute/commit paradigm (also known as evaluate/update) using delta cycles.
Delta cycle: a complete compute/commit cycle that does not advance global time.
Zero-delay models generate new events at the current time, tnow. To avoid shoot-through, these need to be delayed until all current evaluation is complete. Models write such events to the next field of the signal and such writes add the signal to the pending list.
Raw EDS without deltacycles
while (eventlist <> EMPTY)
{ e = hd eventlist;
eventlist = tl eventlist;
tnow = e.time;
e.net.current = e.value;
for (m in e.net.models) do m.exec()
}
| EDS kernel with pending queue (simplified):
while (eventlist <> EMPTY)
{ e = hd eventlist;
if (e.time > tnow) and (pending<>EMPTY)
{ // Commit pendings and commence new delta cycle
for (net in pending) do net.current=net.next;
pending = EMPTY;
for (n in nets just updated) for (m in n.models) m.exec();
} else
{ eventlist = tl eventlist;
tnow = e.time;
e.net.current = e.value;
for (m in e.net.models) do m.exec();
}
}
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Summary algorithm:
Details fully lectured by MJCG (slide 110 onwards): »Temporal Logic Course
| 37: (C) 2008-17, DJ Greaves, University of Cambridge, Computer Laboratory. | Flash Player Upgrade Needed
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