There are many combinational circuits that have the same functionality.
Synthesis tools can accept additional guiding metrics from the user, that affect
Our basic 3-step recipe did not have an optimisation function weighted by such metrics.
Gate libraries have high and low drive stength forms of most gates (see later). The synthesis tool will chose the appropriate gate depending on the fanout and (estimated) net length during routing.
Some leaf cells are broadside and do not require bit-blasting.
The tool will use Quine/McCluskey, Espresso or similar for logic minimisation. Liberal use of the `x' don't care designation in the source RTL allows the synthesis tool freedom to perform this logic minimisation.
reg[31:0] y; ... if (e1) y <= e2; else if (e3) y <= e4; else y <= 32'bx; // Note, assignment of 'x' permits automated logic minimisation.
Can share sub-expressions or re-compute expressions locally. Reuse of sub-expressions is important for locally-derived results, but with today's VLSI, sending a 32 bit addition result more than one millimeter on the chip may use more power then recomputing it locally!
Logic synthesis is an underconstrained optimisation problem. Both choosing what cubes to use in a Boolean expression and finding which subexpressions are useful when generating several output functions are exponentially complex. Iteration and hill climbing must be used.
Also, we can sometimes re-encode state so that output function is simple to decode (covered in ABD notes not lectured this year but critical for HLS where the controlling sequencer hugely benefits).
(The most famous logic synthesiser is Design Compiler from Synopsys which has been used for the majority of today's chips.)
| 25: (C) 2008-17, DJ Greaves, University of Cambridge, Computer Laboratory. |
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