On-chip Busses Summary.

Multiplexing using tri-states is common at the PCB level but active multiplexors result in less wire being charged and so are used on-chip to save energy.

It is handy if all of the IP blocks to be integrated conform to a common bus bus port standard.

Automatic synthesis of glue logic and memory maps is possible (see HLS section of these notes, if lectured).

Formal specifications of bus ports are widely used, assisting in tool automation and ABD.

The AMBA AHB bus from ARM Cambridge was widely used: but is quite complex (e.g. when resuming from a split burst transaction) and was intolerant of additional pipeline stages being inserted between initiator and responder (i.e. had no temporal decoupling).

The OCP BVCI supports temporal decoupling, but requests and responses must not overtake: hence it can cross clock domains and tolerate pipeline stages. But it cannot tolerate re-ordered responses (e.g. from a DRAM).

Full AXI includes tokens/tags on each operation so support out-of-order request/response association. This suits many advanced initiators and targets, but on-chip networks must preserve transaction ordering within an tag value to avoid WaW hazards.