The counter/timer channel is essentially a counter that counts internal clock pulses or external events and which interrupts the processor on a certain count value.
An automatic re-load register accommodates poor interrupt latency, so that the processor does not need to re-load the counter before the next event.
The counter/timer block will have perhaps 8 such channels. One is commonly dedicated as the system watchdog that performs a hard reboot if not serviced within some tmie out by the CPU (e.g. 500 ms).
Timer (illustrated in the RTL) : counts pre-scaled system clock, but a counter has external inputs as shown on the schematic (e.g. car rev counter).
Four to eight, versatile, configurable counter/timers generally provided in one block.
All registers also configured as bus slave read/write resources for programmed I/O.
In this example, the interrupt is cleared by host programmed I/O (during host_op).
| 34: (C) 2008-17, DJ Greaves, University of Cambridge, Computer Laboratory. |