DRAM & Controller (2).

DRAM controller is typically coupled with a cache or at least a write buffer.

DRAM: high latency and write-back overhead dictate preference for large burst operations.

The best controllers will lookahead in a pool of pending requests to assist decisions on when to do write back (aka close or deactivate). It is normal to prioritise reads over writes, but overtaking must be avoided or else reads can be served from the write queue.

But a new request falling in a previously open line can arrive just after we closed it!

It is best if clients can tolerate responses out-of-order (hence use bus/NoC structure that supports this).

Controller must

• set up DRAM control register programming,
• set clock frequency and calibrate delay lines,
• implement specific RAS-to-CAS latencies and many other timing details,
• and ensure refresh happens.

Controller often contains a tiny CPU to interrogate serial device data.

DRAM refresh overhead has minimal impact on bus throughput. For example, if 512 refresh cycles are needed in 4 ms and the cycle rate is 200E6 the overhead is 0.1 percent.

In the memories folder there is a simple DRAM+Controller TLM model. In the dramsim2 folder there is a TLM wrapper around the Univ-Maryland DRAM simulator. (Not examinable for CST).

Hardware is normally programmable in terms of physical address interleave. An example is, starting with most significant in physical address space: bank, row, col, burst offset, byte lane. Byte lane and burst offset are always at the bottom and col is kept lower than row, but having bank lower than col gives interleaving of accesses to open pages which is sensible when the system workload has a lot of localised activity to one large area, whereas having bank higher makes sense when the system has various concurrent active hot spots, such as typical with heap, stack, code and static segments. etc..

Here we are using the definition of a bank as a region where only one row is active within one bank. Multiple banks may be within the same channel (which always occurs for banks within one DRAM chip) or arranged over separate channels were a channel is defined as a data bus (or DRAM controller backside port). Multiple channles gives higher data throughput owing to spatial diversity.