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90 Nanometer Gate Length.

The mainstream VLSI technology in the period 2004-2008 was 90 nm.

Now the industry is using 35-45 nanometer and smaller (but yield problems).

Parameters from a 90 nanometer standard cell library:
Parameter Value Unit
Drawn Gate Length 0.08 µm
Metal Layers 6 to 9 layers
Max Gate Density 400K gates/mm²
Finest Track Width 0.25 µm
Finest Track Spacing 0.25 µm
Tracking Capacitance 1 fF/mm
Core Supply Voltage 0.9 to 1.4 V
FO4 Delay 51 ps
Leakage current nA/gate

Typical processor core: 200k gates + 4 RAMs: one square millimeter.

Typical SoC chip area is 50-100 mm² → 20-40 million gates (semi-custom/standard cell).

Actual gate and transistor counts are higher owing to full-custom blocks (RAMs mainly).

» Moore's Law » Transistor Count

6: (C) 2008-13, DJ Greaves, University of Cambridge, Computer Laboratory.