How to generate clock enable conditions ?
A clock is `needed' if any register will change on a clock edge.
If not a straightforward pipeline, need to be sure there are no `oscillating' stages that retrigger themselves or an `earlier' stage (add further runtime checks or else statically know their maximum settling time and use a counter).
Save further power: shortly we look at dynamic frequency and voltage scaling.
17: (C) 2008-13, DJ Greaves, University of Cambridge, Computer Laboratory. |