Everybody attending this course is expected to have previously studied RTL coding or at least taught themselves the basics before the course starts.
The Computer Laboratory has an online Verilog course you can follow: »Cambridge SystemVerilog Tutor
Please note that this now covers `System Verilog' whereas most of my examples are in plain old Verilog. There are some (unimportant) syntax differences.
|7: (C) 2008-13, DJ Greaves, University of Cambridge, Computer Laboratory.|