READY
Two coding styles (it does not matter whether these transfers are each in their own always statement or share over whole clock domain):
always @(posedge clk) a <= b ? c + d;
always @(posedge clk) b <= c - d;
always @(posedge clk) c <= 22-c;
|
always @(posedge clk) begin
a <= b ? c + d;
b <= c - d;
c <= 22-c;
end
|
In System Verilog we would use always_ff in the above cases.
Typical example (illustrating pure RT forms):
module CTR16(
input mainclk,
input din,
output o); // Note handout uses older syntax here
reg [3:0] count, oldcount;
// Add a four bit decimal value of one to count
always @(posedge mainclk) begin
count <= count + 1;
if (din) oldcount <= count; // Is `if' pure ?
end
// Note ^ is exclusive-or operator
assign o = count[3] ^ count[1];
endmodule
Registers are assigned in clock domains (one shown called `mainclk').
In a stricter form of this pure RTL, we cannot use `if', so when we want a register to sometime retain its current value we must assign this explicitly, leading to forms like this:
oldcount <= (din) ? count : oldcount;
| 13: (C) 2008-13, DJ Greaves, University of Cambridge, Computer Laboratory. | Flash Player Upgrade Needed
READY
|
|