SystemC: Abstracted Signals

Signals have a current value and a next value. Assigns are to the next value whereas reads use the current value. The next value is copied to the current value in a commit cycle when there are no futher events of the current tnow on the event queue.

For faster system modelling, we do not want to enter EDS kernel for every change of every net or bus: so is it possible to pass larger objects around, or even send threads between components, like S/W does ?

Yes, it is possible to put any datatype inside a signal and route that signal between components (provided the datatype can be checked for equality to see if current and next are different and so on). Using this approach, a higher-level model is possible, because a complete Ethernet frame or other large item can be delivered as a single event, rather than having to step though the cycle-by-cycle operation of a serial hardware implementation.

Even better: SystemC 2.0 enabled threads to be passed along the channels, allowing intermodule thread calling, just like object-oriented software. This will enable TLM modelling (described later). Hence we have three inter-module communication styles:

1. Pin-level modelling: an event is a change of a net or bus,
2. Abstract data modelling: an event is delivery of a complete cache line or other data packet,
3. Transactional-level modelling: avoid events as much as possible: use intermodule software calling.