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Validation using Simulation

The alternative to formal verification is validation using extensive simulation and overnight testing of the day's work using regression testing.

Tests can be unit tests or larger subsystems or complete system (H/W + S/W).

Can either write a RTL or ESL yes/no automaton as part of the test bench,

or spool outputs to file and diff against golden with PERL script.

Downfall of simulation: it's non-exhaustive and time consuming.

ABD benefits (and challenges):

But: Simulations

3: (C) 2008-13, DJ Greaves, University of Cambridge, Computer Laboratory.