SRAM example: first define the socket in the .h file:
SC_MODULE(cbgram) { tlm_utils::simple_target_socketport0; ...
Here is the constructor:
cbgram::cbgram(sc_module_name name, uint32_t mem_size, bool tracing_on, bool dmi_on): sc_module(name), port0("port0"), latency(10, SC_NS), mem_size(mem_size), tracing_on(tracing_on), dmi_on(dmi_on) { mem = (uint8_t *)malloc(mem_size); // allocate memory // Register callback for incoming b_transport interface method call port0.register_b_transport(this, &cbgram::b_access); }
And here is the guts of b_access:
void cbgram::b_access(tlm::tlm_generic_payload &trans, sc_time &delay) { tlm::tlm_command cmd = trans.get_command(); uint32_t adr = (uint32_t)trans.get_address(); uint8_t * ptr = trans.get_data_ptr(); uint32_t len = trans.get_data_length(); uint8_t * lanes = trans.get_byte_enable_ptr(); uint32_t wid = trans.get_streaming_width(); if (cmd == tlm::TLM_READ_COMMAND) { ptr[0] = mem[adr]; } else ... trans.set_response_status( tlm::TLM_OK_RESPONSE); }
Wire up the ports in the level above:
busmux0.init_socket.bind(memory0.port0);
The full code is in the OR1K btlm-ref-design folder.
19: (C) 2008-13, DJ Greaves, University of Cambridge, Computer Laboratory. |