General Interrupt Structure

Nearly all devices have a master interrupt enable control flag that can be set and cleared by under programmed I/O by the controlling processor. Its output is just ANDed with the local interrupt source.

We saw its use in the UART device driver, where transmit interrupts are turned off when there is nothing to send.

The programmed I/O uses the write enable (hwen) signal to guard the transfer of data from the main data bus into the control register. A hren signal is used for reading back stored value (shown on later slides).

The principal of programming is (see UART device driver):

• Receiving device: Keep interrupt enabled: device interrupts when data ready.
• Transmit device: Enable interrupt when S/W output queue non-empty: device interrupts when H/W output queue has space.

With only a single interrupt wire to the processor, all interrupt sources share it and the processor must poll around on each interrupt to find the device that needs attention.

Enchancement: a vectored interrupt makes the processor branch to a device-specific location.

Interrupts can also be associated with priorities, so that interrupts of a higher level than currently being run preempt.