A current-day system on a chip (SoC) consists of several different microprocessor subsystems together with memories and I/O interfaces. This course covers SoC design and modelling techniques with emphasis on architectural exploration, assertion-driven design and the concurrent development of hardware and embedded software. This is the ``front end'' of the design automation tool chain. (Back end material, such as design of individual gates, layout, routing and fabrication of silicon chips is not covered.)
A percentage of each lecture is used to develop a running example. Over the course of the lectures, the example evolves into a System On Chip demonstrator with CPU and bus models, device models and device drivers. All code and tools are available online so the examples can be reproduced and exercises undertaken. The main languages used are Verilog and C++ using the SystemC library.
This course has six main topics (SG1-SG6) with an optional final section on high-level synthesis (SG7) to be lectured if time permits.
In addition to these topics, the running example will demonstrate a few practical aspects of device bus interface design, on chip communication and device control software. Students can run the examples on PWF or their own machine (please ask for links).
|1: (C) 2008-13, DJ Greaves, University of Cambridge, Computer Laboratory.|