In the last few years, Bluespec System Verilog has successfully raised the level of abstraction in RTL design in the industry.
module mkTb (Empty); Reg#(int) x <- mkReg (23); rule countup (x < 30); int y = x + 1; x <= x + 1; $display ("x = %0d, y = %0d", x, y); endrule rule done (x >= 30); $finish (0); endrule endmodule: mkTb
Second example uses a pipeline object that could have aribtrary delay. Sending process is blocked by implied handshaking wires (hence less typing than Verilog) and in the future would allow the programmer or the compiler to retime the implementation of the pipe component.
module mkTb (Empty); Reg#(int) x <- mkReg ('h10); Pipe_ifc pipe <- mkPipe; rule fill; pipe.send (x); x <= x + 'h10; endrule rule drain; let y = pipe.receive(); $display (" y = %0h", y); if (y > 'h80) $finish(0); endrule endmodule
But, behavioural expressing using a conceptual thread is also useful to have!