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Dynamic Power Gating

Increased tendency towards multi-product platform chips means large functional blocks on silicon may be off for complete product lifetime.

Battery powered, portable devices can also use macro-scale block power down (e.g. the audio or video input and output subsystems).

Dynamic clock gating can be fairly fine grain, but we can also turn off power to sections of logic (coarser grain).

Use power gating cells in series with supply rails.

And use signal isolation and retention cells (t-latches) on data input and output nets.

No register and RAM data retention in block while off.

Dynamic power gating techniques typically require some sequencing: several clock cycles to power up/down a region.

Generally, power off/on controlled by software or top-level input pads.

Sometimes power off a whole chip except for a one or two RAMs and register files.

Can also retain volatile contents using a lower supply while clock is off (CMOS RAM data holding voltage).

»Fujitsu Article: Design of low power consumption LSIs

45: (C) 2008-11, DJ Greaves, University of Cambridge, Computer Laboratory.